Programming Massively Parallel Processors (PMPP)
Summer Semester 2008
This lecture covers the foundations of programming massively parallel processors. It is focussed on the architecture of modern graphics hardware and its use for non-graphics applications.
The lecture will be complemented by practical programming exercises.
Course Description
Graphic cards have traditionally been used (or misused) for applications besides rendering. Applications could benefit from the massive compute power and the special purpose hardware available on the graphics cards. This required, however, mapping the algorithm on the individual stages of the rendering pipeline in an often tedious process. Recent architectural changes remove many of these restrictions. Newly available programming tools allow for high-level, straightforward programming of these systems.
The course will provide a theoretical and practical introduction into the topic. The lectures will discuss the basic architecture of modern graphics cards and their use for general purpose computing. They will furthermore discuss relevant algorithms and programming techniques for massively parallel processors. The exercises will be practical programming exercises based on NVIDIAs CUDA framework.
Lecturer: Prof. Dr.-Ing. Michael Goesele
Teaching Assistant: Mate Beljan
More information can be found in the course's Module-Guide listing and the corresponding forum.
Please register as soon as possible for the course using the department's webreg system (e.g., using the direct link to the PMPP registration). Registration is open until April 11, 2008!
Time and Location
Lectures: Monday 11.40 – 13.20 in Room 074 in the Fraunhofer IGD building (S3|05, directions)
Note Room Change:: The lecture on May 5th will beheld in Room 073 (just to the left of the normal location)!
Exercises: Tuesday 9.50 – 11.30 in Room 074 in the Fraunhofer IGD building (S3|05, directions)
Exercises
The lecture is accompanied by mandatory programming exercises. We will provide a sufficient number of machines with CUDA capable hardware installed. We plan to implement a bonus system for the exercises. Details will be announced later.
Preliminary Schedule
| Date | Lecture | Exercises | Reading |
7.4.2008 |
Introduction (PDF) | --- |
Berkeley Report, Chapter 1-3 (web site, local copy) |
14.4.2008 |
CUDA Programming Model (PDF) | ||
21.4.2008 |
CUDA Programming Model 2 (PDF) | ||
28.4.2008 |
CUDA Performance Features (PDF) | CUDA Programming Guide, Chapters 1-3 and 5 | |
5.5.2008 |
Introduction Final Projects (list of final projects) | --- |
|
12.5.2008 |
--- | ||
19.5.2008 |
Parallel Programming (updated PDF) | Preface — Chapter 2 in Mattson et al. | |
26.5.2008 |
Design Patterns (PDF) | Chapter 3 in Mattson et al. | |
2.6.2008 |
Design Patterns 2 (PDF) | Chapter 4 in Mattson et al. | |
9.6.2008 |
Design Patterns 3 (PDF) | Chapters 5 and 6 in Mattson et al. | |
16.6.2008 |
Summary (PDF) | ||
23.6.2008 |
Guest Lecture: Adaptive Computer (PDF) | ||
30.6.2008 |
Final Project Presentations (PDF) |
Note: You will need username and password to access the slides and files above. Please contact Michael Goesele or Mate Beljan if you participate in the lecture but do not have the access information.
Office Hours
By appointment. Please contact me via email or contact my secretary Carola Eichel.
Prerequisites
- solid programming experience in C/C++
- basic algorithms and data structures
Literature and Web References
- Hubert Nguyen:
GPU Gems 3, Addison Wesley - T. Mattson, B. Sanders, B. Massingill:
Patterns for Parallel Programming, Addison Wesley - gpgpu.org - General-Purpose Computation Using Graphics Hardware
- NVIDIA CUDA page
- Krste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams and Katherine A. Yelick:
The Landscape of Parallel Computing Research: A View from Berkeley, Technical Report No. UCB/EECS-2006-183, University of California at Berkeley - ...
